1. Field of the Invention
The present invention relates to phase interpolation devices and slew rate control devices thereof.
2. Description of the Related Art
In a computing system, data may be transmitted by a data stream, and at least one clock signal is available in the computing system for recovering data from the data stream. However, there may be a delay while transmitting the data stream, so that a phase shift may occur between the data stream and the clock signal. When the phase shift exceeds an allowable limit, a phase interpolation technique is required in the computing system to generate new clock signals with phases different from the available clock signals.
FIG. 1A shows a conventional phase interpolation circuit, which comprises two logic gates LG1 and LG2. The logic gates LG1 and LG2 may be inverters or current mode logic circuits (CML circuits) or any circuits capable of buffering the input signals. As shown, clock signals clki and clkq (originally provided in the computing system, where clki is an in-phase clock signal and clkq is a quadrature clock signal, and the quadrature clock signal clkq lags behind the in-phase clock signal clki by 90 degrees) are input to the logic gates LG1 and LG2, respectively, and the output terminals of the logic gates LG1 and LG2 are connected together to provide a phase interpolated signal clknew. Compared with the clock signals clki and clkq, the phase interpolated signal clknew lags behind the in-phase clock signal clki and leads the quadrature clock signal clkq.
The structure of the logic gate LG1 may be identical to that of the logic gate LG2. For such cases, FIG. 1B depicts the phase difference between the clock signals clki and clkq and the phase interpolated clock signal clknew. As shown, the phase of the phase interpolated signal clknew is read according to the reference line 102. The phase interpolated signal clknew lags behind the in-phase clock signal clki by 45 degrees and leads the quadrature clock signal clkq by 45 degrees.
However, the phase interpolation circuits can only handle clock signals rising or falling at limited speeds. If the clock signals rise or fall faster than a threshold speed, the phase interpolation circuits may fail to generate the phase interpolated clock signal. Thus, phase interpolation devices with slew rate control techniques are called for.